India Approves Semicon 2.0: A 1.275 Trillion Rupee Push for Semiconductor Leadership

The Indian government has officially approved the second phase of its national semiconductor strategy, designated as Semicon 2.0. Backed by a substantial budgetary outlay of 1.275 trillion Indian Rupees, which equals approximately 2.15 trillion Japanese Yen or 15 billion US Dollars, this comprehensive initiative marks a major shift from building basic fabrication capacity to nurturing a fully integrated domestic semiconductor ecosystem.

Building upon the foundation laid by Semicon 1.0, which successfully greenlit 12 semiconductor fabrication and packaging projects totaling over 1.64 trillion Rupees in cumulative investment alongside 24 chip design projects, the updated program addresses the broader value chain. Key milestones from the first phase include commercial operations commencing at three major facilities, including Micron Technology's packaging plant in Gujarat, with additional commercial production lines scheduled to go live by late 2026.

Semicon 2.0 focuses on six strategic core pillars designed to eliminate supply chain bottlenecks and establish long-term technological independence:

1. Semiconductor Design Expansion: Deepening the startup ecosystem by supporting custom chip architecture, intellectual property creation, and system-on-chip development for commercial and strategic applications.

2. Equipment, Materials, and Specialty Chemicals: Incentivizing global and local manufacturers of semiconductor fabrication equipment, high-purity process gases, and critical materials like silicon substrates and gallium nitride.

3. Advanced Fabrication Facilities: Expanding manufacturing beyond conventional silicon CMOS nodes into compound semiconductors, discrete devices, and display fabrication.

4. Advanced Packaging and OSAT: Strengthening Assembly, Testing, Marking, and Packaging facilities with a focus on high-density 3D packaging, fan-out wafer-level packaging, and advanced heterogeneous integration.

5. Strategic Research and Development: Transitioning from mature nodes ranging from 28 nanometers to 110 nanometers toward next-generation miniaturization and advanced lithography research.

6. Workforce and Academic Talent Development: Scaling cleanroom operational training and electronic design automation tools across more than 300 universities to build a highly skilled engineering workforce.

Through this balanced allocation across infrastructure, equipment, design, and talent, India aims to position itself as an indispensable regional hub in the global semiconductor supply chain.